1. Field of the Invention
The present disclosure generally relates to complex gate-all-around (GAA) field effect transistor (FET) devices at advanced technology nodes, and, more particularly, to GAA FET devices on SOI (silicon-on-insulator) type substrates.
2. Description of the Related Art
In modern electronic equipment, integrated circuits (ICs) experience a vast applicability in a continuously spreading range of applications. In particular, the demand for increasing mobility of electronic devices at high performance and low energy consumption drives developments to more and more compact devices having features with sizes significantly smaller than 1 μm, the more so as current semiconductor technologies are apt of producing structures with dimensions in the magnitude of 100 nm or less. With ICs representing a set of electronic circuit elements integrated on a semiconductor material, normally silicon, ICs may be made much smaller than any discreet circuit composed of separate independent circuit components. Indeed, the majority of present-day ICs are implemented by using a plurality of circuit elements, such as field effect transistors (FETs), also called metal oxide semiconductor field effect transistors or MOSFETs, occasionally also simply referred to as MOS transistors, and passive elements, such as resistors, e.g., diffusion resistors, and capacitors, integrated on a semiconductor substrate within a given surface area. Typical present-day ICs involve millions of single circuit elements formed on a semiconductor substrate.
The basic function of a MOSFET is that of an electronic switching element, controlling a current through a channel region provided between two junction regions which are referred to as source and drain. The control of the conductivity state of the channel region is achieved by means of a gate electrode which is disposed over the channel region and to which a voltage relative to source and drain is applied. In common planar MOSFETs, the channel region extends in a plane between source and drain. Generally, in applying a voltage exceeding a characteristic voltage level to the gate electrode, the conductivity state of the channel is changed, and switching between a conducting state or “ON-state” and a non-conducting state or “OFF-state” may be achieved. It is important to note that the characteristic voltage level at which the conductivity state changes (usually called the “threshold voltage”), therefore, characterizes the switching behavior of the MOSFET and it is a general issue to keep variations in the threshold voltage level low for implementing a well-defined switching characteristic. However, with the threshold voltage depending nontrivially on the transistor's properties, e.g., materials, dimensions, etc., the implementation of a desired threshold voltage value during fabrication processes involves careful adjustment and fine tuning during the fabrication processes, which makes the fabrication of complex semiconductor devices by advanced technologies more and more difficult.
In general, it was observed that, with the sizes of individual MOSFETs having steadily decreased over the last decades, strongly scaled MOSFETs more and more suffered from undesirable effects once the length of the channel of a MOSFET entered the same order of magnitude as the width of the depletion layer of source and drain. For strongly scaled MOSFETs, for example, the OFF-state leakage current (i.e., the leakage current during the OFF-state) increased with the idle power required by the device. Accordingly, these deteriorating effects, which appear at small scales and are associated with a short channel length, are frequently referred to as so-called “short channel effects.” In order to continue to lower scales, tremendous efforts are needed to address the issues or marginalities, variabilities and challenges appearing in scaling towards VLSI (very large scale integration) MOSFET technologies at, for instance, 20 nm or less, such that all the marginalities in each individual process step and all variabilities are properly addressed and, at best, reduced.
In the efforts of overcoming the above-described issues encountered when reaching smaller and smaller scales, multi-gate MOSFET devices have been proposed. A kind of multi-gate MOSFET device used for advanced 22/14 nm technologies is realized as a so-called “FinFET.” In general, FinFETs represent three-dimensional transistors formed by thin fins extending upwardly from a semiconductor substrate, where particularly the transistor's channel is three-dimensional. For example, in some designs of FinFET devices, the channel is formed along the vertical sidewalls of the fin (which is also referred to as a “double-gate transistor”) or along the vertical sidewall surfaces and the upper horizontal surface of the fin (leading to so-called “tri-gate transistors”). Double-gate transistors and tri-gate transistors have wide channels and, on the other hand, high performance, which can be achieved without substantially increasing the area of the substrate surface required by these transistors because a transistor's performance, being measured by its transconductance, is proportional to the width of the transistor channel. Therefore, by the multi-gate configuration provided by the three-dimensional channel of FinFETs, these semiconductor devices allow for a better control of the channel region when compared to common planar transistor devices.
In order to reach the next generation technology nodes, i.e., at nodes smaller than 14 nm, e.g., 10 nm/7 nm, new device concepts are currently under evaluation, such as field effect transistor devices or FET devices of the gate-all-around (GAA) type. Basically, GAA FETs are similar in concept to FinFETs except that the gate material surrounds the channel region on all sides of the channel. GAA FETs are expected to have a reduced leakage current and power consumption when compared to conventional FinFET devices due to the enhanced gate control implemented by a gate of the GAA type as, opposed to the gate control achieved in FinFET devices, the gate of FinFET devices “only” controls the channel from three sides. However, at present, a consistent concept of fabricating GAA FETs at advanced technology nodes has not been proposed, particularly smaller than 10 nm/7 nm.
Therefore, it is desirable to provide a method of forming a semiconductor device and a semiconductor device for implementing GAA FET structures at advanced technology nodes.